So you have the latest snapdragon 8 gen 1 or Dimensity 9000 or the upcoming Apple M2?
All of these latest processing chips are made in high-tech foundries at 4nm.
nm (nanometer) is a COMMERCIAL -Marketing unit used by chip manufacturing companies. It tells us how closely packed transistors are inside the processor.
Not to be taken literally.
All chips are made up of transistors (bipolar/field effect) that act as a switch for a certain voltage. ex low voltage = 0, high voltage = 1. More transistors= more functionality(addition, subtraction, multiplication, division etc). combination of all we call a mobile /inverter/ radio/tv/computer.
I.e. there are billions of transistors living in one chip: distance between them (channel length, fin pitch (the gap between transistors) & gate pitch (the gap between gates) is what companies are refereeing to with nm units. so compared to the 4nm process, 3nm process has
Less gap = less distance to cover for the electrons = faster operations=less energy expense=low heat generation and dissipation problem=small die size=lower overall cost after industry adapts= more money per chip.
since we are already at 4nm and 3 and 2 nm planned in next 5 years. let’s look at how far this can go on or opportunities that exist for us humans, in the obstacles that this world provides.
HEAT
Heat = excited particles will always be a by-product of everything mechanical and electronic. i.e. from resistance to flow of electrons (flow of information) through-silicon paths in transistors, leading to voltage drop which in turn requires increasing current to maintain the voltage gap. if this is not sufficient, high heat = high resistance=higher the draw= higher number of errors= premature failure.
Fact: i3, i5 processors could be those i7s which didn’t make it out of quality gates of intel.
which is why small die size=less nm process = low power consumption=low dist=low heat.
but with lowering distances
we transition from the classical stochastic realm to the quantum realm.
Lt(processing power)= f(probability of tunneling, timeline)
According to Moore’s observation (axiom), electronic devices will double in speed and capability every two years. i.e. what we are witnessing now.
from vacuum tubes, we have come a long way in shrinking them. Transistors are supposed to be on-off switches; if we continuously shrink the gates and their gaps, there will be leakage. Even with the switch off, there will be a little bit of current= electron escape = data loss.
These losses will be gradual when we consider the density at such a level of miniaturization. = data losses due to difference in way data moves in and out of memory= unpredictable/unexpected changes in electrical signals=varying effective dielectric thickness.
with shrinking sizes, high dielectric constant gate materials are losing their sheen due to shrinking gate oxides resulting in more leakages.
A study suggests that probability of quantum tunneling which was relatively insignificant till 2021,
will raise exponentially up to 2.68% in 2025.
Real problem
The problem is we don’t even have the processing power to simulate the quantum realm and take action; although analytical models are there)
With the recent transition from Finfets (silicon fin on 3sides, bottom connected to silicon) to gate all around FETs (nanosheets- gate surrounds channel region in entirety)) the bottom side leakage= heat= data loss seems to be reduced. but when we look at the bigger picture, nothing signiticant changes except the complexity of process.
(4nm FINFet)= more data loss * less transistor density.
(3/2nm GAAfet/MBC FEt)= lesser data loss * high transistor density, increased complexity of finding the right materials and designing them.
Evolving up ahead, into the realm of verticalfets/complementary fets or stacked fets. Here are some of the gaps we need to overcome :
- New lithography (from EUV)
2. upgrading design process(deposition and removal technologies)
3. wiring -connection upgrade (too congested wiring requires new materials)
4.defect detection tech for denser layouts
5.hybrid scaling or heterogeneous integration
If history repeats itself, all the commercial chipmakers will stick to the traditional existing process and evolve it,
until someone like musk bhaiyya (or he himself) arrives on the scene and deep dives into the quantum realm.
Starts mass-producing QFETS/QWFETS in turn accelerating qubit tech and politically imposing quantum supremacy.
This pops up in my head, while ending this article.
contrary to Moore’s law, this is mine (leelas axiom)
In upcoming years,
More complicated technology =
more techno political influencers =More people stuck in the web of tech=
exponential decline in quality of food
= lower levels of satisfaction in people.
Whoever made this world,
doesn’t want to be found,
he made all of this for you( you + all other living creatures living here). Enjoy in the little time you get to live. Doing simple things.
Conclusion:
if there is a 2.68% quantum tunneling probability in a stochastic computer, imagine how much amount is being generated in our brain along with associated losses and the amount of junk I need to consume to power it. (since i don’t have time to grow my own)
Now you know why people move to the Himalayas. Do not overthink! cooling systems don’t work on us humans. Even after all of this, the quest for unknown is going to remain the most exiting part of being a human.